Configuration Jumpers - Epson S1D13504 Technical Manual

Page 10

3.2 Configuration Jumpers

Jumper Function
JP1 BUSCLK Selection
JP2 CLKI Selection
JP3 CoreVDD current
JP4 IOVDD current
JP5 LCD Panel Voltage
JP6 Panel Enable Polarity
JP7 PCI FPGA enable
S1D13504
X19A-G-014-01
The S5U13504B00C has seven jumper blocks which configure various board settings. The
jumper positions for each function are shown below.
Table 3-2: Jumper Settings
Position 1-2
BUSCLK from U2 oscillator
CLKI from U3 oscillator
Normal operation
Normal operation
+5V LCDVCC
LCDPWR active high
Diable FPGA for non-PCI host
= Default configuration
JP1 - BUSCLK Selection
JP1 selects the source for BUSCLK.
When the jumper is at position 1-2, the BUSCLK source is provided by the oscillator at U2
(default setting).
When the jumper is at position 2-3, the BUSCLK source is provided by the non-PCI host
system.
Note
When used in a PCI environment, JP1 must be set to the 1-2 position.
Figure 3-2: Configuration Jumper (JP1) Location
Position 2-3
BUSCLK from H2 header
CLKI is the same as BUSCLK
n/a
n/a
+3.3V LCDVCC
LCDPWR active low
n/a
JP1
BUSCLK from
BUSCLK
Oscillator (U2)
from H2
S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
Jumper Off
n/a
n/a
Current measurement for
CoreVDD
Current measurement for
IOVDD
n/a
n/a
Enable FPGA for PCI host
Issue Date: 2002/12/02