Table 7-28: Tft A.c. Timing; Vancouver Design Center - Epson S1D13504 Technical Manual

Page 84
Symbol
FPSHIFT period
t1
FPSHIFT pulse width high
t2
FPSHIFT pulse width low
t3
data setup to FPSHIFT falling edge
t4
data hold from FPSHIFT falling edge
t5
FPLINE cycle time
t6
FPLINE pulse width low
t7
t8
FPFRAME cycle time
t9
FPFRAME pulse width low
t10
horizontal display period
t11
FPLINE setup to FPSHIFT falling edge
FPFRAME falling edge to FPLINE falling edge
t12
phase difference
t13
DRDY to FPSHIFT falling edge setup time
t14
DRDY pulse width
t15
DRDY falling edge to FPLINE falling edge
t16
DRDY hold from FPSHIFT falling edge
t17
FPLINE Falling edge to DRDY active
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t6 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts
min
3. t7 = [((REG[07h] bits [3:0])+1)*8] Ts
min
4. t8 = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [5:0])+1)] lines
min
5. t9 = [((REG[0Ch] bits [2:0])+1)] lines
min
6. t10 = [((REG[04h] bits [6:0])+1)*8] Ts
min
7. t12 = [((REG[06h] bits [4:0])+1)*8] Ts
min
8. t14 = [((REG[04h] bits [6:0])+1)*8] Ts
min
9. t15 = [((REG[06h] bits [4:0])+1)*8 - 2] Ts
min
10. t17 = [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)*8 + 2]
min
S1D13504
X19A-A-002-19

Table 7-28: TFT A.C. Timing

Parameter
Epson Research and Development
Min Typ
1
0.45
0.45
0.45
0.45
note 2
note 3
note 4
note 5
note 6
0.45
note 7
0.45
note 8
note 9
0.45
note 10
Hardware Functional Specification

Vancouver Design Center

Max Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
250 Ts
Issue Date: 01/11/06