Appendix A Supported Panel Values - Epson S1D13504 Technical Manual

Epson Research and Development
Vancouver Design Center

Appendix A Supported Panel Values

A.1 Supported Panel Values
Passive
4-Bit Single
Register
320X240@60Hz
Monochrome
REG[02h] 0000 0000
REG[03h] 0000 0000
REG[04h] 0010 0111
REG[05h] 0001 0000
REG[08h] 1110 1111
REG[09h] 0000 0000
REG[0Ah] 0000 0001
REG[0Dh] 0000 1101
REG[19h] 0000 0110
REG[24h] 0000 0000
REG[26h]
load LUT
REG[27h] 0000 0000
Register
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[08h]
REG[09h]
REG[0Ah]
REG[0Dh]
REG[19h]
REG[1Bh]
REG[24h]
REG[26h]
REG[27h]
Programming Notes and Examples
Issue Date: 01/02/01
The following tables show related register data for different panels. All the examples are based on
8 bpp, 40MHz pixel clock and 2M bytes of 60 ns EDO-DRAM.
Table 9-1: Passive Single Panel
Passive Passive
8-Bit Single 8-Bit Single
320X240@60Hz 640X480@60Hz
Color Monochrome
0001 0100 0001 0000
0000 0000 0000 0000
0010 0111 0100 1111
0001 0000 0000 0101
1110 1111 1101 1111
0000 0000 0000 0001
0000 0001 0000 0001
0000 1101 0000 1101
0000 0110 0000 0001
0000 0000 0000 0000
load LUT load LUT
0000 0000 0000 0000
Table 9-2: Passive Dual Panel
Passive
Passive
8-Bit Dual
8-Bit Dual
640X480@60Hz
640X480@60Hz
Color
Monochrome
0001 0010 0001 0110
0000 0000 0000 0000
0100 1111 0100 1111
0000 0101 0000 0101
1110 1111 1110 1111
0000 0000 0000 0000
0000 0001 0000 0001
0000 1101 0000 1101
0000 0011 0000 0011
0000 0000 0000 0000
0000 0000 0000 0000
load LUT load LUT
0000 0000 0000 0000
Passive
Passive
8-Bit Single 16-Bit Single
640X480@60Hz 640X480@47Hz
Color
Color
0001 0100 0010 0100
0000 0000 0000 0000
0100 1111 0100 1111
0000 0101 0000 0101
1101 1111 1101 1111
0000 0001 0000 0001
0000 0001 0000 0001
0000 1101 0000 1101
0000 0001 0000 0001
0000 0000 0000 0000
load LUT load LUT
0000 0000 0000 0000
Passive
16-Bit Dual
640X480@60Hz
Color
0010 0110
0000 0000
set horizontal display width
0100 1111
set horizontal non-display period
0000 0101
set vertical display height bits 7-0
1110 1111
set vertical display height bits 9-8
0000 0000
set vertical non-display period
0000 0001
set 8 bpp and LCD enable
0000 1101
set MCLK and PCLK divide
0000 0011
enable half frame buffer
0000 0000
set Look-Up Table address to 0
0000 0000
load Look-Up Table
load LUT
set Look-Up Table to bank 0
0000 0000
Notes
set panel type
set MOD rate
set horizontal display width
set horizontal non-display period
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set 8 bpp and LCD enable
set MCLK and PCLK divide
set Look-Up Table address to 0
load Look-Up Table
set Look-Up Table to bank 0
Notes
set panel type
set MOD rate
Page 61
S1D13504
X19A-G-002-07