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2.1.3 Burst Cycles
2.2 Chip-Select Module
S1D13504
X19A-G-011-07
Burst cycles are very similar to normal cycles, except they occur as a series of four back-
to-back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output asserted
continuously through the burst. Burst memory cycles are mainly intended to facilitate cache
line fill from program or data memory. They are typically not used for transfers to/from IO
peripheral devices such as the S1D13504. The MCF5307 chip selects provide a mechanism
to disable burst accesses for peripheral devices which are not able to support them.
In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select
Module can generate active-low Output Enable (OE) and Write Enable (WE) signals
compatible with most memory and x86-style peripherals. The MCF5307 bus controller also
provides a Read/Write (R/W) signal which is compatible with most 68K peripherals.
Chip selects 0 and 1 can be programmed independently to respond to any base address and
block size. Chip select 0 can be active immediately after reset, and is typically used to
control a boot ROM. Chip select 1 is typically used to control a large static or dynamic
RAM block.
Chip selects 2 through 7 have fixed block sizes of 2M bytes each. Each has a unique, fixed
offset from a common, programmable starting address. These chip selects are well-suited
to typical IO addressing requirements.
Each chip select may be individually programmed for:
• Port size (8/16/32-bit).
• Number of wait states (0-15) or external acknowledge.
• Address space type.
• Burst or non-burst cycle support.
• Write protect.
Epson Research and Development
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor
Vancouver Design Center
Issue Date: 01/02/02
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