Normal (Non-Burst) Bus Transactions - Epson S1D13504 Technical Manual

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2.2.1 Normal (Non-Burst) Bus Transactions

TSIZ[0:1], AT[0:3]
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/10/26
A data transfer is initiated by the bus master by placing the memory address on address
lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several
control signals are also provided with the memory address:
• TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit.
• RD/WR -- set high for read cycles and low for write cycles.
• AT[0:3] (Address Type Signals) -- provides more detail on the type of transfer being
attempted.
When the peripheral device being accessed has completed the bus transfer, it asserts TA
(Transfer Acknowledge) for one clock cycle to complete the bus transaction. Once TA has
been asserted, the MPC821 will not start another bus cycle until TA has been de-asserted.
The minimum length of a bus transaction is two bus clocks.
The following figure illustrates a typical memory read cycle on the Power PC system bus.
SYSCLK
TS
TA
A[0:31]
RD/WR
D[0:31]
Transfer Start Wait States
Figure 2-1: Power PC Memory Read Cycle
Sampled when TA low
Transfer Next Transfer
Complete Starts
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