Epson S1D13504 Technical Manual page 177

Epson Research and Development
Vancouver Design Center
Register
REG[04h]
REG[05h]
REG[06h]
REG[07h]
REG[08h]
REG[09h]
REG[0Ah]
REG[0Bh]
REG[0Ch]
REG[0Dh]
REG[19h]
REG[24h]
REG[26h]
REG[27h]
REG[2Ch]
REG[2Eh]
Programming Notes and Examples
Issue Date: 01/02/01
Table 6-4: Related register data for Simultaneous Display
640X480@75Hz 640X480@60Hz
PCLK=40.0MHz PCLK=40.0MHz
0100 1111 0100 1111
0001 1101 0001 0011
0000 0011 0000 0001
0000 0111 0000 1011
1000 1111 1101 1111
0000 0001 0000 0001
0010 1100 0010 1100
0000 0000 0000 1001
1000 0010 0000 0001
0000 1111 0000 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
program program
RAMDAC RAMDAC
Notes
set horizontal display width
set horizontal non-display period
set HSYNC start position
set HSYNC polarity and pulse width
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set VSYNC start position
set VSYNC polarity and pulse width
set 8 bpp and CRT enable
set MCLK and PCLK divide
set look-up table address to 0
load look-up table
set look-up table to bank 0
set write mode address to 0
load RAMDAC palette data
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S1D13504
X19A-G-002-07