Memory Interface; Table 5-2: Memory Interface Pin Descriptions - Epson S1D13504 Technical Manual

Page 24

5.4.2 Memory Interface

Pin Name Type
F00A
F01A
LCAS# O 50
UCAS# O 49
WE# O 48
RAS# O 47
67, 65,
63, 61,
59, 57,
55, 53,
MD[15:0] IO
52, 54,
56, 58,
60, 62,
64, 66
S1D13504
X19A-A-002-19

Table 5-2: Memory Interface Pin Descriptions

Pin #
Reset = 0
Driver
Value
F02A
56 CO1 Output 1
55 CO1 Output 1
54 CO1 Output 1
53 CO1 Output 1
76, 70,
68, 66,
64, 62,
60, 58, Hi-Z
CD2/TS1
59, 61, (pulled 0)
63, 65,
67, 69,
75, 77
Description
This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the lower byte (LCAS#).
• For single CAS# DRAM, this is the column address strobe
(CAS#).
See Table 5-10: "Memory Interface Pin Mapping," on page 32
for summary.
This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the upper byte (UCAS#).
• For single CAS# DRAM, this is the write enable signal for the
upper byte (UWE#).
See Table 5-10: "Memory Interface Pin Mapping," on page 32
for summary.
This pin has multiple functions.
• For dual CAS# DRAM, this is the write enable signal (WE#).
• For single CAS# DRAM, this is the write enable signal for the
lower byte (LWE#).
See Table 5-10: "Memory Interface Pin Mapping," on page 32
for summary.
Row address strobe.
These pins have multiple functions.
• Bi-directional memory data bus.
• During reset, these pins are inputs and their states at the
rising edge of RESET# are used to configure the chip.
Internal pull-down resistors (typical values of
100KΩ/100KΩ/120KΩ at 5.0V/3.3V/3.0V respectively) pull
the reset states to 0. External pull-up resistors can be used
to pull the reset states to 1. See Section 5.5, "Summary of
Configuration Options" on page 30.
Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/11/06