Clock Input Requirements; Memory Interface Timing; Edo-Dram Read Timing; Table 7-6: Clock Input Requirements - Epson S1D13504 Technical Manual

Page 46

7.2 Clock Input Requirements

Clock Input Waveform
V
IH
V IL
Symbol
T Input Clock Period (CLKI)
CLKI
T Pixel Clock Period (PCLK) not shown
PCLK
T Memory Clock Period (MCLK) not shown
MCLK
t Input Clock Pulse Width High (CLKI)
PWH
t Input Clock Pulse Width Low (CLKI)
PWL

7.3 Memory Interface Timing

7.3.1 EDO-DRAM Read Timing

Memory
Clock
MA
RAS#
CAS#
MD(Read)
S1D13504
X19A-A-002-19
t
PWH

Figure 7-6: Clock Input Requirements

Table 7-6: Clock Input Requirements

Parameter
Note
When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).
There is no minimum frequency for CLKI.
t1
t3 t4
R
t10 t11
t12

Figure 7-7: EDO-DRAM Read Timing

t
PWL
T
CLKI
Min
12.5
25
25
45%
45%
t2
t5 t7
t6
C1 C2 C3
t15
t13
d1 d2
Epson Research and Development
Vancouver Design Center
Typ Max
55%
55%
t8 t9
C4
t14
t16
d3 d4
Hardware Functional Specification
Issue Date: 01/11/06
Units
ns
ns
ns
T
CLKI
T
CLKI