Figure 3-3: Typical System Diagram - Mc68K Bus 2, 256Kx16 Fpm/Edo-Dram (32-Bit Mc68030); Figure 3-4: Typical System Diagram - Generic Bus, 1Mx16 Fpm/Edo-Dram; Vancouver Design Center - Epson S1D13504 Technical Manual

Epson Research and Development

Vancouver Design Center

MC68030
BUS
A[31:21]
FC0, FC1
A[20:0]
D[31:16]
DS#
AS#
R/W#
SIZ1
SIZ0
DSACK1#
BCLK
RESET#
Figure 3-3: Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
GENERIC
BUS
A21
CSn#
A[20:0]
D[15:0]
WE0#
WE1#
RD0#
RD1#
WAIT#
BCLK
RESET#
Hardware Functional Specification
Issue Date: 01/11/06
Power
Management
M/R#
Decoder
CS#
Decoder
AB[20:0]
DB[15:0]
WE1#
BS#
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#
Power
Management
M/R#
CS#
AB[20:0]
DB[15:0]
WE0#
WE1#
RD#
RD/WR#
WAIT#
BUSCLK
RESET#
Figure 3-4: Typical System Diagram – Generic Bus, 1Mx16 FPM/EDO-DRAM
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
S1D13504
FPFRAME
FPLINE
LCDPWR
256Kx16
FPM/EDO-DRAM
.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
S1D13504
FPFRAME
FPLINE
LCDPWR
1Mx16
FPM/EDO-DRAM
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
Display
FPFRAME
FPLINE
DRDY
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
FPFRAME Display
FPLINE
DRDY
MOD
X19A-A-002-19
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S1D13504