Epson S1D13504 Technical Manual page 425

Color graphics lcd/crt controller

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5.2 Hardware Description—Using Two IT8368E's

PR31500/PR31700

LHA23/MFIO10

Notes: The Chip Select Logic shown above is necessary to guarantee the timing parameter t1

of the Generic MPU Host Bus Interface Asynchronous Timing (for details refer to the S1D13504 Hardware

Functional Specification , document number X19A-A-002-xx).

When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset

the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 5-2: S1D13504 to PR31500/PR31700 Connection using Two IT8368E

Interfacing to the Philips MIPS PR31500/PR31700 Processor

Issue Date: 01/10/26

The following implementation uses a second IT8368E, not in VGA mode, in place of an

address latch. The pins LHA23 and LHA[20:13] provide the latch function instead.

Clock divider

System RESET

X19A-G-005-09

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