Table 8-8: Pixel Panning Selection; Vancouver Design Center - Epson S1D13504 Technical Manual

Page 100
Memory Address Offset Register 0
REG[16h]
Memory Memory
Address Address
Offset Bit 7 Offset Bit 6
Memory Address Offset Register 1
REG[17h]
n/a n/a
REG[16] bits 7-0
REG[17] bits 1-0
Pixel Panning Register
REG[18h]
Screen 2 Screen 2
Pixel Panning Pixel Panning
Bit 3 Bit 2
Number of Bits-Per-Pixel
bits 7-4
bits 3-0
S1D13504
X19A-A-002-19
Memory Memory
Address Address
Offset Bit 5 Offset Bit 4
n/a n/a
Memory Address Offset Bits [9:0]
These bits are the 10-bit address offset from the starting word of line "n" to the starting word of line
"n + 1". This value is applied to both screen 1 and screen 2.
Note
This value is in words and must be programmed ≥ REG[04h].
A virtual image can be formed by setting this register to a value greater than the width of the dis-
play. The displayed image is a window into the larger virtual image.
See Section 10, "Display Configuration" on page 115 for details.
Screen 2 Screen 2
Pixel Panning Pixel Panning
Bit 1 Bit 0
This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each screen
can be independently panned to the left by programming its respective Pixel Panning Bits to a non-
zero value. This value represents the number of pixels panned. The maximum pan value is dependent
on the display mode as shown in the table below.

Table 8-8: Pixel Panning Selection

1
2
4
8
15/16
Smooth horizontal panning can be achieved by a combination of this register and the Display Start
Address register. See Section 10, "Display Configuration" on page 115 and S1D13504
Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details.
Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
Memory Memory
Address Address
Offset Bit 3 Offset Bit 2
n/a n/a
b
Screen 1 Screen 1
Pixel Panning Pixel Panning
Bit 3 Bit 2
Screen 2 Pixel Panning Bits Used
Bits [3:0]
Bits [2:0]
Bits [1:0]
Bit 0
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Vancouver Design Center

Memory Memory
Address Address
Offset Bit 1 Offset Bit 0
Memory Memory
Address Address
Offset Bit 9 Offset Bit 8
Screen 1 Screen 1
Pixel Panning Pixel Panning
Bit 1 Bit 0
Hardware Functional Specification
Issue Date: 01/11/06
RW
RW
RW