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ARM9TDMI Processor Core Memory Interface
3-8
The size of the transfer is indicated by DMAS[1:0]. These signals become valid at
approximately the same time as the data address bus. The encoding is given below in
Table 3-4:
For coprocessor transfers, access to memory is not required, but there will be a transfer
of data between the ARM9TDMI and coprocessor using the data buses, DD[31:0] and
DDIN[31:0]. DnRW indicates the direction of the transfer and DMAS[1:0] indicates
word transfers, as all coprocessor transfers are word sized.
The DMORE signal is active during load and store multiple instructions and only ever
goes HIGH when DnMREQ is LOW. This signal effectively gives the same
information as DSEQ, but a cycle ahead. This information is provided to allow external
logic more time to decode sequential cycles.
Figure 3-3 on page 3-9 shows a load multiple of four words followed by an MCR,
followed by an aborted store. Note the following:
•
The DMORE signal is active in the first three cycles of the load multiple to
indicate that a sequential word will be loaded in the following cycle.
•
From the behavior of InMREQ during the LDM, it can be seen that an instruction
fetch takes place when the instruction enters the execute stage of the pipeline, but
that thereafter the instruction pipeline is stalled until the LDM completes.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table 3-4 DMAS[1:0] encoding
DMAS[1:0]
Transfer size
00
Byte
01
Half word
10
Word
11
Reserved
ARM DDI0145B
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