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Debug Support
5.9
Clock switching during test
5-28
When under serial test conditions, when test patterns are being applied to the core
through the JTAG interface, the ARM9TDMI must be clocked using DCLK. Entry into
test is less automatic than debug and some care must be taken.
On the way into test, GCLK must be held LOW. The TAP controller can now be used
to perform serial testing on the ARM9TDMI. If scan chain 0 and INTEST are selected,
DCLK is generated while the state machine is in RUN-TEST/IDLE state.
During EXTEST, DCLK is not generated.
On exit from test, RESTART must be selected as the TAP controller instruction. When
this is done, GCLK can be allowed to resume. After INTEST testing, care should be
taken to ensure that the core is in a sensible state before switching back. The safest way
to do this is to either select RESTART and then cause a system reset, or to insert
into the instruction pipeline before switching back.
MOV PC,#0
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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