ARM ARM9TDMI Technical Reference Manual page 113

Instruction
STR
LDM
LDM
LDM
STM
STM
SWP
SWP
B, BL, BX
SWI, Undefined
CDP
LDC, STC
MCR
MRC
MRC
MRS
MSR
MSR
MUL, MLA
SMULL, UMULL,
SMLAL, UMLAL
ARM DDI0145B
Instruction
Cycles
bus
1 1S
2 1S+1I
n 1S+(n-1)I
n+4 2S+1N+(n+1)I
2 1S+1I
n 1S+(n-1)I
2 1S+1I
3 1S+2I
3 2S+1N
3 2S+1N
b+1 1S+bI
b+n 1S+(b+n-1)I
b+1 1S+bI
b+1 1S+bI
b+2 1S+(b+1)I
1 1S
1 1S
3 1S + 2I
2+m 1S+(1+m)I
3+m 1S+(2+m)I
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table 7-2 Instruction cycle bus times (continued)
Data bus Comment
1N All cases
1S+1I Loading 1 Register, not the PC
1N+(n-1)S Loading n registers, n > 1, not loading the PC
1N+(n-1)S+4I Loading n registers including the PC, n > 0
1N+1I Storing 1 Register
1N+(n-1)S Storing n registers, n > 1
2N Normal case
2N+1I Loaded byte used by following instruction
3I All cases
3I All cases
(1+b)I All cases
bI+1N+(n-1)S All cases
bI+1C All cases
bI+1C Normal case
(b+I)I+1C Following instruction uses transferred data
1T All cases
1T If only flags are updated (mask_f)
3I If any bits other than just the flags are updated
(all masks other than_f)
(2+m)I All cases
(3+m)I All cases
Instruction Cycle Summary and Interlocks
7-3