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Name
Direction
nRESET
Input
nWAIT
Input
UNIEN
Input
ARM DDI0145B
Description
Not Reset.
This is a level-sensitive input signal which is used to start the processor from a known address.
The ARM9TDMI processor asynchronously enters reset when nRESET goes LOW.
Not Wait.
When a memory request cannot be processed in a single cycle, the ARM9TDMI can be made
to wait for a number of GCLK cycles by driving nWAIT LOW. Internally, the inverse of
nWAIT is ORed with GCLK, and must only change when GCLK is HIGH. If nWAIT is not
used, it must be tied HIGH.
Unidirectional Enable.
When HIGH, all ARM9TDMI outputs are permanently driven, (the state of IABE, DABE,
DDBE and TBE is ignored). The DDIN[31:0] and DD[31:0] buses form a unidirectional data
bus.
When LOW, outputs can go tristate and the DD[31:0] bus is only driven during write cycles.
If DD[31:0] and DDIN[31:0] are wired together, they form a bidirectional data bus.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Signal Descriptions
Table A-6 Miscellaneous signals (continued)
A-11
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