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3.1.1
Wait states
ARM DDI0145B
It is not as critical for the instruction interface to have access to the data memory area
unless the processor needs to execute code from data memory.
For memory accesses which require more than one cycle, the processor can be halted
by using nWAIT. This signal halts the processor, including both the instruction and data
interfaces. The nWAIT signal should be driven LOW by the end of phase 2 to stall the
processor (it is inverted and ORed with GCLK to stretch the internal processor clock).
The nWAIT signal must only change during phase 2 of GCLK. For debug purposes the
internal core clock is exported on the ECLK signal. This timing is shown below in
Figure 3-1.
Alternatively, wait states may be inserted by stretching either phase of GCLK before it
is applied to the processor. ARM9TDMI does not contain any dynamic logic which
relies on regular clocking to maintain its state. Therefore there is no limit on the
maximum period for which GCLK may be stretched, in either phase, or the time for
which nWAIT may be held LOW.
The system designer must take care when adding wait states because the interface is
pipelined. When a wait state is asserted, the current data and instruction transfers are
suspended. However, the address buses and control signals will have already changed
to indicate the next transfer. It is therefore necessary to latch the address and control
signals of each interface when using wait states.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Processor Core Memory Interface
Figure 3-1 ARM9TDMI clock stalling using nWAIT
3-3
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