Table of Contents
Advertisement
4.5
CDP
ARM DDI0145B
CDP signals normally execute in a single cycle. Like all the previous cycles, InMREQ
is driven LOW to signal when an instruction is entering the decode and then the execute
stage of the pipeline:
•
if the instruction really is to be executed, the PASS signal is be driven HIGH
during phase 2 of execute
•
if the coprocessor can execute the instruction immediately it drives CHSD[1:0]
with LAST
•
if the instruction requires a busy-wait cycle, the coprocessor drives CHSD[1:0]
with WAIT and then CHSE[1:0] with LAST.
Figure 4-5 on page 4-14 shows a CDP which is cancelled due to the previous instruction
causing a data abort. The CDP instruction enters the execute stage of the pipeline and
is signalled to execute by PASS. In the following phase LATECANCEL is asserted.
This causes the coprocessor to terminate execution of the CDP instruction and for it to
cause no state changes to the coprocessor.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Coprocessor Interface
4-13
Advertisement
Table of Contents
