Table of Contents
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P
PASS 4-5
PC
return address calculations 5-37
pipeline 2-4
ARM 4-2
coprocessor 4-2
interlock 4-11
interlocks 7-5
pipeline follower 4-2
timing 2-4
processor
halting 3-3
processor core
diagram 1-3
implementation 1-2
processor state
determining 5-29
programmer's model 2-1
protocol converter 5-3
public instructions within debug
BYPASS 5-16
CLAMP 5-16
CLAMPZ 5-17
EXTEST 5-14
HIGHZ 5-16
IDCODE 5-15
INTEST 5-15
SCAN_N 5-15
R
reset
memory interface 3-12
S
scan chains 5-11, 5-22
external 5-21
scan chain 0 5-22
scan chain 0 bit order 6-1, 6-3
scan chain 1 5-23
scan chain 2 5-24
scan chain 3 5-25
serial test and debug 5-12
signals
ARM DDI0145B
coprocessor interface A-5
data memory interface A-3
debug A-8
instruction memory interface A-2
JTAG and TAP controller A-6
miscellaneous A-10
single stepping 5-47
SYSSPEED bit 5-31
system speed
instructions 5-31
system state
determining 5-30
scan chain 1 5-30
T
TAP controller 5-11, 5-12, 5-21
TAP state machine 5-26
test
clock switching 5-28
system reset 5-28
test data registers 5-19
ARM9TDMI device ID code register
5-19
bypass register 5-19
instruction register 5-20
scan chain select register 5-20
scan chains 5-22
testing 6-1
EXTEST 6-2
parallel and serial 6-2
scan chain 0 bit order 6-3
test patterns 6-2
Thumb instruction set 1-2
timing
diagrams 8-2
parameters 8-14
U
unidirectional write data data bus 3-10
V
vector catching 5-46
Copyright © 1998, 1999 ARM Limited. All rights reserved.
W
wait states 3-3
watchpoints 5-7
exceptions 5-10
timing 5-7
Index
Index-3
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