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5.13.3
Control registers
ARM DDI0145B
The format of the control registers depends on how bit 3 is programmed. If bit 3 is
programmed to be 1, the breakpoint comparators examine the data address, data and
control signals.
In this case, the format of the register is as shown in Figure 5-10.
Note
Bit 8 and bit 3 cannot be masked.
Figure 5-10 Watchpoint control register for data comparison
The bits have the following functions:
Table 5-5 Watchpoint control register for data comparison bit functions
Bit
Function
DnRW
Compares against the data not read/write signal from the core in order to
detect the direction of the data data bus activity. nRW is 0 for a read, and 1
for a write.
DMAS[1:0]
Compares against the DMAS[1:0] signal from the core in order to detect the
size of the data data bus activity.
DnTRANS
Compares against the data not translate signal from the core in order to
determine between a user mode (DnTRANS = 0) data transfer, and a
privileged mode (DnTRANS = 1) transfer.
EXTERN
Is an external input into the EmbeddedICE macrocell that allows the
watchpoint to be dependent upon some external condition. The EXTERN
input for watchpoint 0 is labelled EXTERN0, and the EXTERN input for
watchpoint 1 is labelled EXTERN1.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Debug Support
5-41
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