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ARM9TDMI Coprocessor Interface
4-10
that the instruction has now been issued to the execute stage. If the condition codes pass,
and hence the instruction is to be executed, the PASS signal is driven HIGH and the
CHSD[1:0] handshake bus is examined (it is ignored in all other cases). For any
successive execute cycles the CHSE[1:0] handshake bus is examined. When the LAST
condition is observed, the instruction is committed. In the case of an MCR, the
DD[31:0] bus is driven with the register data. In the case of an MRC, DDIN[31:0] is
sampled at the end of the ARM9TDMI memory stage and written to the destination
register during the next cycle.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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