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Timing parameter
Tdckd
Tdckh
Tddbe
Tddbz
Tddend
Tddenh
Tddh
Tddod
Tddoh
Tdds
Tdgid
Tdgih
Tdih
Tdis
Tdlkd
Tdlkh
Tdmqd
Tdmqh
Tdmrd
Tdmrh
Tdmsd
Tdmsh
Tdnmd
Tdnmh
Tdqen
ARM DDI0145B
Description
DBGACK output delay
DBGACK output hold time
Delay from DDBE rising to DD[31:0] (output) driven valid
Delay from DDBE falling to DD[31:0] (output) high impedance
DDEN delay from GCLK falling
DDEN hold time from GCLK falling
DD[31:0] (input) hold time from GCLK falling
DD[31:0] (output) delay from GCLK falling
DD[31:0] (output) hold time from GCLK falling
DD[31:0] (input) setup time to GCLK falling
DBGRQI output delay from TCK falling
DBGRQI output hold time from TCK falling
TDI and TMS hold time from TCK rising
TDI and TMS setup time to TCK rising
DLOCK delay from GCLK rising
DLOCK hold time from GCLK rising
DnMREQ delay from GCLK rising
DnMREQ hold time from GCLK rising
DMORE delay from GCLK rising
DMORE hold time from GCLK rising
DMAS[1:0] delay from GCLK rising
DMAS[1:0] hold time from GCLK rising
DnM[4:0] delay from GCLK rising
DnM[4:0] hold time from GCLK rising
DBGRQI falling delay from DBGEN falling
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table 8-1 ARM9TDMI timing parameters (continued)
ARM9TDMI AC Characteristics
8-15
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