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Debug Support
5.13
EmbeddedICE macrocell
5.13.1
Register map
5-38
The EmbeddedICE macrocell is integral to the ARM9TDMI processor core. It has two
hardware breakpoint/watchpoint units each of which may be configured to monitor
either the instruction memory interface or the data memory interface. Each watchpoint
unit has a value and mask register, with an address, data and control field.
Because the ARM9TDMI processor core has a Harvard Architecture, the user must
specify whether the watchpoint registers examine the instruction or the data interface.
This is specified by bit 3:
•
when bit 3 is set, the data interface is examined
•
when bit 3 is clear, the instruction interface is examined.
There can be no don't care case for this bit because the comparators cannot compare the
values on both buses simultaneously. Therefore, bit 3 of the control mask register is
always clear and cannot be programmed HIGH. Bit 3 also determines whether the
internal Breakpoint or Watchpoint signal should be driven by the result of the
comparison. Figure 5-9 on page 5-40 gives an overview of the operation of the
EmbeddedICE macrocell.
The ARM9TDMI EmbeddedICE macrocell has logic that allows single stepping
through code. This reduces the work required by an external debugger, and removes the
need to flush the instruction cache. There is also hardware to allow efficient trapping of
accesses to the exception vectors. These blocks of logic free the two general-purpose
hardware breakpoint/watchpoint units for use by the programmer at all times.
The general arrangement of the EmbeddedICE macrocell is shown in Figure 5-9 on
page 5-40.
The EmbeddedICE macrocell register map is shown below:
Address
Width
00000
4
00001
5
00010
8
00100
6
00101
32
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table 5-4 ARM9TDMI EmbeddedICE macrocell register map
Function
Debug control
Debug status
Vector catch control
Debug comms control
Debug comms data
ARM DDI0145B
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