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Debug Support
5.6.5
Scan chains 0, 1, 2, and 3
5-22
These allow serial access to the core logic, and to the EmbeddedICE macrocell for
programming purposes. Each scan cell is fairly simple and can perform two basic
functions, capture and shift.
Scan chain 0
Purpose
Primarily for inter-device testing (EXTEST), and testing the core
(INTEST). Scan chain 0 is selected via the SCAN_N instruction.
Length
184 bits.
INTEST allows serial testing of the core. The TAP controller must be placed in the
INTEST mode after scan chain 0 has been selected.
•
During CAPTURE-DR, the current outputs from the core's logic are captured in
the output cells.
•
During SHIFT-DR, this captured data is shifted out while a new serial test pattern
is scanned in, thus applying known stimuli to the inputs.
•
During RUN-TEST/IDLE, the core is clocked. Normally, the TAP controller
should only spend one cycle in RUN-TEST/IDLE. The whole operation may then
be repeated.
EXTEST allows inter-device testing, useful for verifying the connections between
devices in the design. The TAP controller must be placed in EXTEST mode after scan
chain 0 has been selected.
•
During CAPTURE-DR, the current inputs to the core's logic from the system are
captured in the input cells.
•
During SHIFT-DR, this captured data is shifted out while a new serial test pattern
is scanned in, thus applying known values on the core's outputs.
•
During RUN-TEST/IDLE, the core is not clocked.
The operation may then be repeated.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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