Instruction Memory Interface Signals - ARM ARM9TDMI Technical Reference Manual

ARM9TDMI Signal Descriptions
A.1

Instruction memory interface signals

Name Direction
IA[31:1] Output
IABE Input
IABORT Input
ID[31:0] Input
InM[4:0] Output
InMREQ Output
InTRANS Output
ISEQ Output
ITBIT Output
A-2
Description
Instruction Address Bus. This is the processor instruction address bus. It changes when
GCLK is HIGH.
Instruction Address Bus Enable. This is an input which, when LOW, it puts the instruction
address bus, IA[31:0], drivers into a high impedance state. This signal has the same effect on
InTRANS and InM[4:0].
If UNIEN is HIGH this signal is ignored.
Instruction Abort. This is an input which allows the memory system to tell the processor that
the requested instruction memory access is not allowed.
Instruction Data Bus. This input bus should be driven with the requested instruction data
before the end of phase 2 of GCLK.
Instruction Mode. These signals indicate the current mode of the processor and are in the same
form as the mode bits in the CPSR.
Not Instruction Memory Request.
If LOW at the end of GCLK phase 2, the processor requires an instruction memory access
during the following cycle.
Not Memory Translate.
When LOW, the processor is in user mode.
When HIGH, the processor is in a privileged mode.
Instruction Sequential Address. If HIGH at the end of GCLK phase 2, any instruction
memory access during the following cycle is sequential from the last instruction memory
access.
Instruction Thumb Bit.
When HIGH, the processor is in Thumb state.
When LOW, the processor is in ARM state.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table A-1 Instruction memory interface signals
ARM DDI0145B