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ARM9TDMI Signal Descriptions
Name
Direction
DnMREQ
Output
DnRW
Output
DnTRANS
Output
DSEQ
Output
A-4
Description
Not Data Memory Request. If LOW at the end of GCLK phase 2, the processor
requires a data memory access in the following cycle.
Data not Read, Write.
If LOW at the end of phase 2, any data memory access in the following cycle is a read.
If HIGH, it is a write.
Data Not Memory Translate. If LOW, the next data memory access is to be performed
as a user mode access, if HIGH the data memory access is to performed as a privileged
mode access.
Note that the data memory access mode may differ from the current processor mode.
Data Sequential Address. If HIGH at the end of phase 2, any data memory access in
the next cycle is sequential from the current data memory access.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table A-2 Data memory interface signals (continued)
ARM DDI0145B
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