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Debug Support
5.5
The JTAG state machine
5-12
The process of serial test and debug is best explained in conjunction with the JTAG state
machine. Figure 5-5 shows the state transitions that occur in the TAP controller.
The state numbers are also shown on the diagram. These are output from the
ARM9TDMI on the TAPSM[3:0] bits.
Figure 5-5 Test access port (TAP) controller state transitions
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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