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4.2
LDC/STC
ARM DDI0145B
The number of words transferred is determined by how the coprocessor drives the
CHSD[1:0] and CHSE[1:0] buses. In the example, four words of data are transferred.
Figure 4-1 on page 4-4 shows the ARM9TDMI LDC/STC cycle timing.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Coprocessor Interface
4-3
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