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Debug Support
5.3.4
Watchpoints and exceptions
5.3.5
Debug request
5.3.6
Actions of the ARM9TDMI in debug state
5-10
If there is an abort with the data access as well as a watchpoint, the watchpoint condition
is latched, the exception entry sequence performed, and then the processor enters debug
state. If there is an interrupt pending, again the ARM9TDMI allows the exception entry
sequence to occur and then enters debug state.
A debug request can take place through the EmbeddedICE macrocell or by asserting the
EDBGRQ signal. The request is synchronized and passed to the processor. Debug
request takes priority over any pending interrupt. Following synchronization, the core
will enter debug state when the instruction at the execution stage of the pipeline has
completely finished executing (once memory and write stages of the pipeline have
completed). While waiting for the instruction to finish executing, no more instructions
will be issued to the execute stage of the pipeline.
Once the ARM9TDMI is in debug state, both memory interfaces will indicate internal
cycles. This allows the rest of the memory system to ignore the ARM9TDMI and
function as normal. Since the rest of the system continues operation, the ARM9TDMI
will ignore aborts and interrupts.
The BIGEND signal should not be changed by the system while in debug state. If it
changes, not only will there be a synchronization problem, but the programmer's view
of the ARM9TDMI will change without the knowledge of the debugger. The nRESET
signal must also be held stable during debug. If the system applies reset to the
ARM9TDMI (nRESET is driven LOW), the state of the ARM9TDMI will change
without the knowledge of the debugger.
When instructions are executed in debug state, the ARM9TDMI will change
asynchronously to the memory system outputs (except for InMREQ, ISEQ,
DnMREQ, and DSEQ which change synchronously from GCLK). For example, every
time a new instruction is scanned into the pipeline, the instruction address bus will
change. If the instruction is a load or store operation, the data address bus will change
as the instruction executes. Although this is asynchronous, it should not affect the
system, because both interfaces will be indicating internal cycles. Care must be taken
with the design of the memory controller to ensure that this does not become a problem.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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