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Debug Support
5.14
Vector catching
5-46
The ARM9TDMI EmbeddedICE macrocell contains logic that allows efficient trapping
of fetches from the vectors during exceptions. This is controlled by the Vector catch
register. If one of the bits in this register is set HIGH and the corresponding exception
occurs, the processor enters debug state as if a breakpoint has been set on an instruction
fetch from the relevant exception vector.
For example, if the processor executes a SWI instruction while bit 2 of the Vector catch
register is set, the ARM9TDMI fetches an instruction from location 0x8. The vector
catch hardware detects this access and forces the internal Breakpoint signal HIGH into
the ARM9TDMI control logic. This, in turn, forces the ARM9TDMI to enter debug
state.
The behavior of the hardware is independent of the watchpoint comparators, leaving
them free for general use. The vector catch register is sensitive only to fetches from the
vectors during exception entry. Therefore, if code branches to an address within the
vectors during normal operation, and the corresponding bit in the Vector Catch register
is set, the processor is not forced to enter debug state.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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