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Instruction Cycle Summary and Interlocks
7.1
Instruction cycle times
Instruction
Data Op
Data Op
Data Op
Data Op
LDR
LDR
LDR
LDR
7-2
Key to tables
Symbol
Meaning
b
The number of busy-wait states during coprocessor accesses
m
In the range 0 to 3, depending on early termination
(see Multiplier cycle counts on page 7-4)
n
The number of words transferred in an LDM/STM/LDC/STC
C
Coprocessor register transfer (C-cycle)
I
Internal cycle (I-cycle)
N
Non-sequential cycle (N-cycle)
S
Sequential cycle (S-cycle)
Table 7-2 summarizes the ARM9TDMI instruction cycle counts and bus activity when
executing the ARM instruction set.
Instruction
Cycles
bus
1
1S
2
1S+1I
3
2S + 1N
4
2S + 1N + 1I
1
1S
2
1S+1I
3
1S+2I
5
2S+2I+1N
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table 7-2 Instruction cycle bus times
Data bus
Comment
1I
Normal case, PC not destination
2I
With register controlled shift, PC not destination
3I
PC destination register
4I
With register controlled shift, PC destination
register
1N
Normal case, not loading PC
1N+1I
Not loading PC and following instruction uses
loaded word (1 cycle load-use interlock)
1N+2I
Loaded byte, half-word, or unaligned word used
by following instruction (2 cycle load-use
interlock)
1N+4I
PC is destination register
Table 7-1 Symbols used in tables
ARM DDI0145B
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