Table of Contents
Advertisement
Instruction Cycle Summary and Interlocks
7-6
Now, because a rotation must occur on the loaded data, there is a second interlock cycle.
The behavior on the instruction memory interface is shown in Figure 7-2.
Example 3
In this third example, the following code sequence is executed:
LDM R12,{R1-R3}
ADD R2, R2, R1
The LDM takes three cycles to execute in the memory stage of the pipeline. The ADD
is therefore delayed until the LDM begins its final memory fetch. The behavior of both
the instruction and data memory interface are shown in Figure 7-3 on page 7-7.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Figure 7-2 Two cycle load interlock
ARM DDI0145B
Advertisement
Table of Contents
