ARM ARM9TDMI Technical Reference Manual page 61

General-purpose microprocessors

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5.3.3

Watchpoints

ARM DDI0145B

This means that the instruction which was previously breakpointed is fetched again, and

if the breakpoint is still set, the processor enters debug state once it reaches the execute

stage of the pipeline.

Once the processor has entered debug state, it is important that further interrupts do not

affect the instructions executed. For this reason, as soon as the processor enters debug

state, interrupts are disabled, although the state of the I and F bits in the Program Status

Entry into debug state following a watchpointed memory access is imprecise. This is

necessary because of the nature of the pipeline and the timing of the Watchpoint signal.

After a watchpointed access, the next instruction in the processor pipeline is always

allowed to complete execution. Where this instruction is a single-cycle data-processing

instruction, entry into debug state is delayed for one cycle while the instruction

completes. The timing of debug entry following a watchpointed load in this case is

shown in Figure 5-3 on page 5-8.

Note

Although instruction 5 enters the execute state, it is not executed, and there is no state

update as a result of this instruction. Once the debugging session is complete, normal

continuation would involve a return to instruction 5, the next instruction in the code

sequence which has not yet been executed.

The instruction following the instruction which generated the watchpoint could have

modified the Program Counter (PC). If this has happened, it will not be possible to

determine the instruction which caused the watchpoint. A timing diagram showing

debug entry after a watchpoint where the next instruction is a branch is shown in

Figure 5-4 on page 5-9. However, it is always possible to restart the processor.

Once the processor has entered debug state, the ARM9TDMI core may be interrogated

to determine its state. In the case of a watchpoint, the PC contains a value that is five

instructions on from the address of the next instruction to be executed. Therefore, if on

entry to debug state, in ARM state, the instruction

processor restarted, execution flow would return to the next instruction in the code

sequence.

is scanned in and the

SUB PC, PC, #20

Debug Support

5-7

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