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5.5.1
Reset
5.5.2
Pullup resistors
5.5.3
Instruction register
ARM DDI0145B
The JTAG interface includes a state-machine controller (the TAP controller). In order
to force the TAP controller into the correct state after power-up of the device, a reset
pulse must be applied to the nTRST signal. If the JTAG interface is to be used, nTRST
must be driven LOW, and then HIGH again. If the boundary scan interface is not to be
used, the nTRST input may be tied permanently LOW.
Note
A clock on TCK is not needed to reset the device.
The action of reset is as follows:
1.
System mode is selected. The boundary scan chain cells do not intercept any of
the signals passing between the external system and the core.
2.
The IDCODE instruction is selected. If the TAP controller is put into the Shift-DR
state and TCK is pulsed, the contents of the ID register are clocked out of TDO.
The IEEE 1149.1 standard effectively requires TDI and TMS to have internal pullup
resistors. In order to minimize static current draw, these resistors are not fitted to the
ARM9TDMI. Accordingly, the four inputs to the test interface (the TDO, TDI and
TMS signals plus TCK) must all be driven to valid logic levels to achieve normal circuit
operation.
The instruction register is four bits in length. There is no parity bit. The fixed value
loaded into the instruction register during the CAPTURE-IR controller state is 0001.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Debug Support
5-13
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