Table of Contents
Advertisement
Debug Support
5-50
When the W bit is clear, a message is written by a register transfer to coprocessor 14.
As the data transfer occurs from the processor to the comms data write register, the W
bit is set in the debug comms control register.
The debugger sees a synchronized version of both the R and W bit when it polls the
debug comms control register through the JTAG interface. When the debugger sees the
W bit is set, it can read the comms data write register and scan the data out. The action
of reading this data register clears the debug comms control register W bit. At this point,
the communications process may begin again.
As an alternative to polling, the debug comms channel can be interrupt driven by
connecting the ARM9TDMI COMMRX and COMMTX signals to the systems
interrupt controller.
Receiving a message from the debugger
Message transfer from the debugger to the processor is similar to sending a message to
the debugger. In this case, the debugger polls the R bit of the debug comms control
register.
•
If the R bit is LOW, the comms data read register is free, and data can be placed
there for the processor to read.
•
If the R bit is set, previously deposited data has not yet been collected, so the
debugger must wait.
When the comms data read register is free, data is written there via the JTAG interface.
The action of this write sets the R bit in the debug comms control register.
When the processor polls this register, it sees an MCLK synchronized version. If the R
bit is set, there is data waiting to be collected. This data can be read via an MRC
instruction to coprocessor 14. The action of this load clears the R bit in the debug
comms control register. When the debugger polls this register and sees that the R bit is
clear, the data has been taken, and the process may now be repeated.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
Advertisement
Table of Contents
