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ARM9TDMI Coprocessor Interface
4-6
If a coprocessor instruction busy-waits, PASS is asserted on every cycle until the
coprocessor instruction is executed. If an interrupt occurs during busy-waiting, PASS is
driven LOW, and the coprocessor will stop execution of the coprocessor instruction.
A further output, LATECANCEL, is used to cancel a coprocessor instruction when the
instruction preceding it caused a data abort. This is valid on the rising edge of GCLK
on the cycle that follows the first execute cycle of the coprocessor instructions. This is
the only cycle in which LATECANCEL can be asserted.
On the falling edge of the clock, the ARM9TDMI processor core examines the
coprocessor handshake signals CHSD[1:0] or CHSE[1:0]:
•
If a new instruction is entering the execute stage in the next cycle, it examines
CHSD[1:0].
•
If the currently executing coprocessor instruction requires another execute cycle,
it examines CHSE[1:0].
The handshake signals encode one of four states:
ABSENT
If there is no coprocessor attached that can execute the coprocessor
instruction, the handshake signals indicate the ABSENT state. In this
case, the ARM9TDMI processor core takes the undefined instruction
trap.
WAIT
If there is a coprocessor attached that can handle the instruction, but not
immediately, the coprocessor handshake signals are driven to indicate
that the ARM9TDMI processor core should stall until the coprocessor
can catch up. This is known as the busy-wait condition. In this case, the
ARM9TDMI processor core loops in an idle state waiting for CHSE[1:0]
to be driven to another state, or for an interrupt to occur.
If CHSE[1:0] changes to ABSENT, the undefined instruction trap will be
taken.
If CHSE[1:0] changes to GO or LAST, the instruction will proceed as
described below.
If an interrupt occurs, the ARM9TDMI processor core is forced out of the
busy-wait state. This is indicated to the coprocessor by the PASS signal
going LOW. The instruction will be restarted at a later date and so the
coprocessor must not commit to the instruction (it must not change any
of the coprocessor's state) until it has seen PASS HIGH, when the
handshake signals indicate the GO or LAST condition.
GO
The GO state indicates that the coprocessor can execute the instruction
immediately, and that it requires another cycle of execution. Both the
ARM9TDMI processor core and the coprocessor must also consider the
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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