ARM ARM9TDMI Technical Reference Manual page 148

ARM9TDMI Signal Descriptions
A.6 Miscellaneous signals
Name Direction
BIGEND Input
ECLK Output
nFIQ Input
GCLK Input
HIVECS Input
nIRQ Input
ISYNC Input
A-10
Description
Big-Endian Configuration.
When this input is HIGH, the ARM9TDMI processor treats bytes in memory as being in
big-endian format. When it is LOW, memory is treated as little-endian.
External Clock.
The clock by which the ARM9TDMI is currently being clocked. This clock will reflect any
wait states applied by nWAIT, and once debug state has been entered by the debug clock.
Not Fast Interrupt request.
This input causes the core to be interrupted if taken LOW, and if the appropriate enable in the
processor is active. The signal is level-sensitive and must be held LOW until a suitable
response is received from the processor. The nFIQ signal may be synchronous or
asynchronous, depending on the state of ISYNC.
Clock.
This clock times all ARM9TDMI memory accesses (both data and instruction), and internal
operations. The clock has two distinct phases—phase 1 in which GCLK is LOW and phase 2
in which GCLK is HIGH. The clock may be stretched indefinitely in either phase to allow
access to slow peripherals or memory. Alternatively, nWAIT may be used with a free running
GCLK to stretch phase 2.
High Vectors Configuration.
When LOW, the ARM9TDMI exception vectors start at address 0x00000000 (hexadecimal).
When HIGH, the ARM9TDMI exception vectors start at address 0xFFFF0000.
Not Interrupt Request.
As nFIQ, but with lower priority. May be taken LOW to interrupt the processor when the
appropriate enable is active. The nIRQ signal may be synchronous or asynchronous,
depending on the state of ISYNC.
Synchronous Interrupts.
When LOW, this input indicates that the nIRQ and nFIQ inputs are to be synchronized by the
processor. When HIGH it disables this synchronization for inputs that are already
synchronous.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table A-6 Miscellaneous signals
ARM DDI0145B