Table of Contents
Advertisement
Debug Support
5.12.3
Watchpoint with another exception
5.12.4
Watchpoint and breakpoint
5.12.5
Debug request
5-36
If a watchpoint access simultaneously causes a data abort, the ARM9TDMI will enter
debug state in abort mode. Entry into debug is held off until the core has changed into
abort mode, and fetched the instruction from the abort vector.
A similar sequence is followed when an interrupt, or any other exception, occurs during
a watchpointed memory access. The ARM9TDMI will enter debug state in the mode of
the exception, and so the debugger must check to see whether this happened. The
debugger can deduce whether an exception occurred by looking at the current and
previous mode, (in the CPSR and SPSR), and the value of the PC. If an exception did
take place, the user should be given the choice of whether to service the exception
before debugging.
For example, suppose an abort occurred on a watchpoint access, and ten instructions
had been executed to determine this. The following sequence could be used to return
program execution:
0 EAFFFFF1; B -15 addresses (two's complement)
1 E1A00000; NOP (MOV R0, R0), SYSSPEED bit is set
This will force a branch back to the abort vector, causing the instructions at that location
to be refetched and executed. Note that after the abort service routine, the instruction
that caused the abort and watchpoint will be re-executed. This will cause the watchpoint
to be generated and hence the ARM9TDMI will enter debug state again.
It is possible to have a watchpoint and breakpoint condition occurring simultaneously.
This can happen when an instruction causes a watchpoint, and the following instruction
has been breakpointed. The same calculation should be performed as for Breakpoint on
page 5-35 to determine where to resume. In this case, it will be at the breakpoint
instruction, since this has not been executed.
Entry into debug state via a debug request is similar to a breakpoint, and as for
breakpoint entry to debug state adds four addresses to the PC, and every instruction
executed in debug state adds one.
For example, the following sequence handles a situation in which the user has invoked
a debug request, and decides to return to program execution immediately:
0 EAFFFFFB; B -5 addresses (2's complement)
1 E1A00000; NOP (MOV R0, R0), SYSSPEED bit is set
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
Advertisement
Table of Contents
