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2.1.2
Instruction set extension spaces
ARM DDI0145B
All ARM processors implement the undefined instruction space as one of the entry
mechanisms for the Undefined Instruction Exception. That is, ARM instructions with
opcode[27:25] = 0b011 and opcode[4] = 1 are UNDEFINED on all ARM processors
including the ARM9TDMI and ARM7TDMI.
ARM Architecture v4 and v4T also introduced a number of instruction set extension
spaces to the ARM instruction set. These are:
•
arithmetic instruction extension space
•
control instruction extension space
•
coprocessor instruction extension space
•
load/store instruction extension space.
Instructions in these spaces are UNDEFINED (they cause an Undefined Instruction
Exception). The ARM9TDMI fully implements all the instruction set extension spaces
defined in ARM Architecture v4T as UNDEFINED instructions, allowing emulation of
future instruction set additions.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Programmer's Model
2-3
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