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ARM9TDMI Processor Core Memory Interface
Note
A sequential cycle can occur immediately after an internal cycle.
Figure 3-2 shows the cycle timing for an N followed by an S cycle, where there is a
prefetch abort on the S cycle:
Figure 3-2 Instruction fetch timing
ARM DDI0145B
Copyright © 1998, 1999 ARM Limited. All rights reserved.
3-5
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