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5.10.3
Instructions which may have the SYSSPEED bit set
ARM DDI0145B
After the system speed instructions have been scanned into the instruction data bus and
clocked into the pipeline, the RESTART instruction must be loaded into the TAP
controller. This will cause the ARM9TDMI automatically to resynchronize back to
GCLK when the TAP controller enters RUN-TEST/IDLE state, and execute the
instruction at system speed. Debug state will be reentered once the instruction
completes execution, when the processor will switch itself back to the internally
generated DCLK. When the instruction has completed, DBGACK will be HIGH. At
this point INTEST can be selected in the TAP controller, and debugging can resume.
To determine whether a system speed instruction has completed, the debugger must
look at SYSCOMP (bit 3 of the Debug status register). To access memory, the
ARM9TDMI must access memory through the data data bus interface, as this access
may be stalled indefinitely by nWAIT. Therefore, the only way to determine whether
the memory access has completed is to examine the SYSCOMP bit. When this bit is
HIGH the instruction has completed.
By the use of system speed load multiples and debug store multiples, the state of the
system memory can be passed to the debug host.
The only valid instructions on which to set this bit are:
•
loads
•
stores
•
load multiple
•
store multiple.
When the ARM9TDMI returns to debug state after a system speed access, the
SYSSPEED bit is set HIGH.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Debug Support
5-31
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