Table of Contents
Advertisement
7.2
Interlocks
ARM DDI0145B
Pipeline interlocks occur when the data required for an instruction is not available due
to the incomplete execution of an earlier instruction. When an interlock occurs,
instruction fetches stop on the instruction memory interface of the ARM9TDMI. Four
examples of this are given below.
Example 1
In this first example, the following code sequence is executed:
LDR R0, [R1]
ADD R2, R0, R1
The ADD instruction cannot start until the data is returned from the load. Therefore, the
ADD instruction has to delay entering the execute stage of the pipeline by one cycle.
The behavior on the instruction memory interface is shown in Figure 7-1.
Example 2
In this second example, the following code sequence is executed:
LDRB R0, [R1,#1]
ADD R2, R0, R1
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Instruction Cycle Summary and Interlocks
Figure 7-1 Single load interlock timing
7-5
Advertisement
Table of Contents
