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5.8
Clock switching during debug
ARM DDI0145B
When the ARM9TDMI enters debug state, it must switch from GCLK to DCLK. This
is handled automatically by logic in the ARM9TDMI. On entry to debug state, the
ARM9TDMI asserts DBGACK in the HIGH phase of GCLK. The switch between the
two clocks occurs on the next falling edge of GCLK.
The ARM9TDMI is forced to use DCLK as the primary clock until debugging is
complete. On exit from debug, the core must be allowed to synchronize back to GCLK.
This must be done in the following sequence. The final instruction of the debug
sequence must be shifted into the instruction data bus scan chain, and clocked in by
asserting DCLK. At this point, RESTART must be clocked into the TAP controller
register.
The ARM9TDMI will now automatically resynchronize back to GCLK when the TAP
controller enters the RUN-TEST/IDLE mode and start fetching instructions from
memory at GCLK speed. For more information, refer to Exit from debug state on
page 5-32.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Figure 5-6 Clock switching on entry to debug state
Debug Support
5-27
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