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4.2.1
Coprocessor handshake encoding
ARM DDI0145B
state of the PASS signal before actually committing to the instruction.
For an LDC or STC instruction, the coprocessor instruction drives the
handshake signals with GO when two or more words still need to be
transferred. When only one further word is to be transferred, the
coprocessor drives the handshake signals with LAST.
In phase 2 of the execute stage, the ARM9TDMI processor core outputs
the address for the LDC/STC. Also in this phase, DnMREQ is driven
LOW, indicating to the memory system that a memory access is required
at the data end of the device. The timing for the data on DD[31:0] for an
LDC and DD[31:0] for an STC is shown in Figure 4-1 on page 4-4.
LAST
An LDC or STC can be used for more than one item of data. If this is the
case, possibly after busy waiting, the coprocessor drives the coprocessor
handshake signals with a number of GO states, and in the penultimate
cycle LAST (LAST indicating that the next transfer is the final one). If
there was only one transfer, the sequence would be
[WAIT,[WAIT,...]],LAST.
For both MRC and STC instructions, the DDIN[31:0] bus is owned by the coprocessor,
and can hence be driven by the coprocessor from the cycle after the relevant instruction
enters the execute stage of the coprocessor pipeline, until the next instruction enters the
execute stage of the coprocessor pipeline. This is the case even if the instruction is
subject to a LATECANCEL or the PASS signal is not asserted.
For efficient coprocessor design, an unmodified version of GCLK should be applied to
the execution stage of the coprocessor. This will allow the coprocessor to continue
executing an instruction even when the ARM9TDMI pipeline is stalled.
Table 4-1 shows how the handshake signals CHSD[1:0] and CHSE[1:0] are encoded.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Coprocessor Interface
Table 4-1 Handshake signals
CHSD/E[1:0]
ABSENT
10
WAIT
00
GO
01
LAST
11
4-7
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