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Debug Support
5.10.2
Determining system state
5-30
After determining the values in the current bank of registers, it may be desirable to
access banked registers. This can only be done by changing mode. Normally, a mode
change may only occur if the core is already in a privileged mode. However, while in
debug state, a mode change from any mode into any other mode may occur. Note that
the debugger must restore the original mode before exiting debug state.
For example, assume that the debugger has been asked to return the state of the user
mode and FIQ mode registers, and debug state was entered in supervisor mode.
The instruction sequence could be:
STMIA R0, {R0-R15}; Save current registers
MRS R0, CPSR
STR R0, [R0]; Save CPSR to determine current mode
BIC R0, R0, #0x1F; Clear mode bits
ORR R0, R0, #0x10; Select USER mode
MSR CPSR, R0; Enter USER mode
STMIA R0, {R13-R14}; Save registers not previously visible
ORR R0, R0, #0x01; Select FIQ mode
MSR CPSR, R0; Enter FIQ mode
STMIA R0, {R8-R14}; Save banked FIQ registers
All these instructions are said to execute at debug speed. Debug speed is much slower
than system speed since between each core clock, 67 scan clocks occur in order to shift
in an instruction, or shift out data. Executing instructions more slowly than usual is fine
for accessing the core's state since the ARM9TDMI is fully static. However, this same
method cannot be used for determining the state of the rest of the system.
While in debug state, only the following instructions may be inserted into the instruction
pipeline for execution:
•
all data processing operations
•
all load, store, load multiple and store multiple instructions
•
MSR and MRS.
To meet the dynamic timing requirements of the memory system, any attempt to access
system state must occur synchronously. Therefore, the ARM9TDMI must be forced to
synchronize back to system speed. The 33rd bit of scan chain 1, SYSSPEED, controls
this.
A legal debug instruction may be placed in the instruction data bus of scan chain 1 with
bit 33 (the SYSSPEED bit) LOW. This instruction will then be executed at debug speed.
To execute an instruction at system speed, a NOP (such as
in as the next instruction with bit 33 set HIGH.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
) must be scanned
MOV R0, R0
ARM DDI0145B
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