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Name
Direction
SHCLK1BS
Output
SHCLK2BS
Output
TAPID[31:0]
Input
TAPSM[3:0]
Output
TCK
Input
TCK1
Output
TCK2
Output
TDI
Input
TDO
Output
nTDOEN
Output
TMS
Input
nTRST
Input
ARM DDI0145B
Description
Boundary Scan Shift Clock Phase 1. This control signal is provided to ease the
connection of an external boundary scan chain. SHCLK1BS is used to clock the master
half of the external scan cells. When the state machine is in SHIFT-DR state, scan chain
3 is selected, SHCLK1BS follows TCK1. When not in the SHIFT-DR state, or when
scan chain 3 is not selected, this clock is LOW. When an external boundary scan chain
is not connected, this output must be left unconnected.
Boundary Scan Shift Clock Phase 2. This control signal is provided to ease the
connection of an external boundary scan chain. SHCLK2BS is used to clock the slave
half of the external scan cells. When the state machine is in SHIFT-DR state, scan chain
3 is selected, SHCLK2BS follows TCK2. When not in the SHIFT-DR state, or when
scan chain 3 is not selected, this clock is LOW. When an external boundary scan chain
is not connected, this output must be left unconnected.
TAP Identification. The value on this bus will be captured when using the IDCODE
instruction on the TAP controller state machine.
TAP Controller State Machine. This bus reflects the current state of the TAP controller
state machine. These bits change off the rising edge of TCK.
The JTAG clock (the test clock).
TCK, Phase 1. TCK1 is HIGH when TCK is HIGH, although there is a slight phase
lag due to the internal clock non-overlap.
TCK, Phase 2. TCK2 is HIGH when TCK is LOW, although there is a slight phase lag
due to the internal clock non-overlap.
Test Data Input, the JTAG serial input.
Test Data Output, the JTAG serial output.
Not TDO Enable. When LOW, this signal denotes that serial data is being driven out
on the TDO output. The nTDOEN signal would normally be used as an output enable
for a TDO pin in a packaged part.
Test Mode Select. TMS selects to which state the TAP controller state machine should
change.
Not Test Reset. Active-low reset signal for the boundary scan logic. This pin must be
pulsed or driven LOW after power up to achieve normal device operation, in addition
to the normal device reset (nRESET).
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table A-4 JTAG and TAP controller signals (continued)
ARM9TDMI Signal Descriptions
A-7
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