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Instruction Cycle Summary and Interlocks
7-8
The code is the same code as in example 3, but in this instance the ADD instruction uses
R3. Due to the nature of load multiples, the lowest register specified is transferred first,
and the highest specified register last. Because the ADD is dependent on R3, there must
be a further cycle of interlock while R3 is loaded. The behavior on the instruction and
data memory interface is shown in Figure 7-4.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Figure 7-4 LDM dependent interlock
ARM DDI0145B
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