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Timing parameter
Tiad
Tiah
Tibkh
Tibks
Tidh
Tids
Timqd
Timqh
Tinmd
Tinmh
Tinth
Tints
Tinxd
Tinxh
Tirsd
Tirsh
Tisqd
Tisqh
Tisyh
Tisys
Titbd
Titbh
Titrsd
Titrsh
Tltcd
ARM DDI0145B
Description
IA[31:1] delay from GCLK rising
IA[31:1] hold time from GCLK rising
IEBKPT hold time from GCLK rising
IEBKPT setup time to GCLK rising
ID[31:0] hold time from GCLK falling
ID[31:0] setup time to GCLK falling
InMREQ delay from GCLK rising
InMREQ hold time from GCLK rising
InM[4:0] delay from GCLK rising
InM[4:0] hold time from GCLK rising
Interrupt (nFIQ/nIRQ) hold time from GCLK falling
Interrupt (nFIQ/nIRQ) setup time to GCLK falling
INSTREXEC output delay
INSTREXEC output hold time
IREG[3:0]/SCREG[4:0] output delay from TCK falling
IREG[3:0]/SCREG[4:0] hold time from TCK falling
ISEQ delay from GCLK rising
ISEQ hold time from GCLK rising
ISYNC hold time from GCLK falling
ISYNC setup time to GCLK falling
ITBIT delay from GCLK rising
ITBIT hold time from GCLK rising
InTRANS delay from GCLK rising
InTRANS hold time from GCLK rising
LATECANCEL delay from GCLK falling
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table 8-1 ARM9TDMI timing parameters (continued)
ARM9TDMI AC Characteristics
8-17
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