Table of Contents
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Index
cycle encoding 3-7
data abort vector 3-7
data cycle 3-7
direction 3-7
endian configuration 3-11
endian effects 3-11
memory access sizes 3-11
size 3-8
size encoding 3-8
16-bit 3-11
32-bit 3-11
8-bit 3-11
DBGACK 5-32
debug
clock switching 5-27
communications channel 5-48
debug scan chain 5-23
entered from ARM state 5-29
entered from Thumb state 5-29
hardware extensions 5-2, 5-4
instruction register 5-13
public instructions 5-14
pullup resistors 5-13
reset 5-13
scan chains 5-22
speed 5-30
state-machine controller 5-13
debug host 5-3
debug interface
signals 5-5
standard 5-2
TAP controller states 5-2
debug request 5-10
debug state 5-2, 5-30
actions of ARM9TDMI 5-10
breakpoints 5-5
exiting 5-32
watchpoints 5-7
debug system 5-3
E
EmbeddedICE 5-5, 5-38
accessing hardware registers 5-24
control registers 5-41
debug control register 5-44
debug status register 5-44
functionality 5-38
Index-2
hardware 5-38
register map 5-38
single stepping 5-47
vector catch register 5-45
vector catching 5-46
EmbeddedICE macrocell 5-1, 5-2,
5-10
EmbeddedICE watchpoint units
debugging 5-11
programming 5-11
testing 5-11
endian effects
data transfer 3-11
instruction fetches 3-6
external scan chains 5-21
F
five-stage pipeline 2-4
H
halting
data interface 3-3
instruction interface 3-3
processor 3-3
I
implementation options 2-2
instruction cycle
counts and bus activity 7-2
data bus instruction times 7-4
multiplier cycle counts 7-4
times 7-2
instruction fetch
aborted 3-4
endian effects 3-6
in ARM state 3-6
in Thumb state 3-6
prefetch abort vector 3-4
timing 3-4
16-bit 3-6
32-bit 3-6
instruction interface
accessing data memory 3-3
Copyright © 1998, 1999 ARM Limited. All rights reserved.
instruction address bus 3-4
instruction fetch timing 3-4
instruction set
ARM 1-2
Thumb 1-2
instruction set extension spaces 2-3
interlocks 2-4, 7-5
LDM dependent timing 7-8
LDM timing 7-6
single load timing 7-5
two cycle load timing 7-6
J
JTAG interface 5-11, 5-13, 5-28
JTAG state machine 5-12
L
LATECANCEL 4-6
M
memory accesses 3-2
coprocessor transfer 3-2
internal 3-2
non-sequential 3-2
sequential 3-2
memory configurations
big-endian 3-2
little-endian 3-2
selecting 3-2
memory interface
accesses 3-2
addressing 3-2
data interface 3-1
instruction interface 3-1
performance 3-2
reset behavior 3-12
N
nRESET 3-12
nWAIT 3-3
ARM DDI0145B
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