Table 1-3. Suggested Chrp Memory Map - Motorola MVME5100 Programmer's Reference Manual

Product Data and Memory Maps
1
Processor Address
Start
0000 0000
top_dram
F400 0000
F800 0000
FC00 0000
FE00 0000
FE80 0000
FEF8 0000
FEF9 0000
FEFF 0000
FF00 0000
FF80 0000
FF90 0000
FFF0 0000
1-6

Table 1-3. Suggested CHRP Memory Map

Size
End
top_dram dram_size
F3FF FFFF 4G-dram_size
F7FF FFFF 64MB
FBFF FFFF 64MB
FDFF FFFF 32MB
FE7F FFFF 8MB
FEF7 FFFF 7.5MB
FEF8 FFFF 64KB
FEFE FFFF 384KB
FEFF FFFF 64KB
FF7F FFFF 8MB
FF8F FFFF 1MB
FFEF FFFF 6MB
FFFF FFFF 1MB
Notes
1. Programmable via Hawk ASIC
2. The actual PowerPlus II size of each ROM/FLASH bank may vary.
3. The first 1MB of ROM/FLASH Bank A appears at this range after
a reset if the rom_b_rv control bit is cleared. If the rom_b_rv control
bit is set this address maps to ROM/FLASH Bank B.
4. The only method to generate a PCI Interrupt Acknowledge cycle
(8259 IACK) is to perform a read access to the Hawks PIACK
Register at 0xFEFF0030.
5. VME should be placed at toe top of PCI memory space.
Definition
System Memory (onboard DRAM)
PCI Memory Space
FLASH Bank A (optional)
FLASH Bank B (optional)
Reserved
PCI/ISA I/O Space
Reserved
System Memory Controller Registers
Reserved
Processor Host Bridge Registers
FLASH Bank A (preferred)
FLASH Bank B (preferred)
Reserved
Boot ROM
Computer Group Literature Center Web Site
Notes
1
1, 5
1, 2
1, 2
1
4
1, 2
1, 2
3