Status Register; Table 1-11. Mvme5100 Status Register - Motorola MVME5100 Programmer's Reference Manual

Product Data and Memory Maps
1

Status Register

REG
BIT
FIELD
OPER
RESET
REQUIRED
OR
OPTIONAL
SYSCON_
BAUDOUT
FUSE
1-24
The MVME5100 implementation of this Register is fully compliant with
the PowerPlus II programming model, with exceptions to bits RD5, RD6
and RD7, as identified in the following table:
An 8-bit status register, accessible through the External Register Set port,
defines the status of the Module.

Table 1-11. MVME5100 Status Register

RD0 RD1 RD2
R R
X X
X X
System Controller Mode bit. If this bit is set, the module is not the
master of its PCI bus (PCI bus 0). If this bit is cleared, the module
is the master of its PCI bus (PCI bus 0). This bit always reads as
cleared ("0").
This is the baud output clock of the TL16C550 UART, referenced
to the 1.8432 MHz UART oscillator. This signal can be used as a
timing reference.
This bit provides the current state of the FUSE signal. If set, at
least one of the planar fuses or polyswitches is open.
Status Register - FEF88080h
RD3 RD4
R R R
X X X
X X X
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RD5 RD6 RD7
R R R
X X 0
O R R